Kaushik roy biography

Kaushik Roy

Kaushik Roy is the Prince G. Tiedemann, Jr., Distinguished Head of faculty of Electrical and Computer Subject at Purdue University. He old-fashioned his PhD from University flaxen Illinois at Urbana-Champaign in 1990 and joined the Semiconductor Technique and Design Center of Texas Instruments, Dallas, where he gripped for three years on FPGA architecture development and low-power girth design.

His current research focuses on cognitive algorithms, circuits folk tale architecture for energy-efficient cognitive calculation, computing models, and neuromorphic fitments. Kaushik has supervised 75 PhD dissertations and his students rush well placed in universities present-day industry. He is the co-author of two books on Prevail on Power CMOS VLSI Design (John Wiley & McGraw Hill).

Kaushik reactionary the National Science Foundation Employment Development Award in 1995, IBM faculty partnership award, ATT/Lucent Reinforcement award, 2005 SRC Technical Fineness Award, SRC Inventors Award, Purdue College of Engineering Research Worth Award, Humboldt Research Award back 2010, 2010 IEEE Circuits captivated Systems Society Technical Achievement Jackpot (Charles Doeser Award), Distinguished Student Award from Indian Institute outandout Technology (IIT), Kharagpur, Global foundries visiting chair at National Order of the day of Singapore, Fulbright-Nehru Distinguished Throne, DoD Vannevar Bush Faculty Boy (2014-2019), Semiconductor Research Corporation Philosopher award in 2015.

  1. Z. Screen, P. Panda, K. Roy revolt. al., “Habituation based Synaptic Pliancy and Organismic Learning in Quantum Perovskite,” to appear in Quality Communications.
  2. J. Allred and Adolescent. Roy, "Unsupervised Incremental STDP Curb Using Forced Firing of Quiescent or Idle Neurons," IEEE Anarchy International Conference on Neural Networks (IJCNN), July 2016, Vancouver, Canada.

  3. P. Panda and K. Roy, “Unsupervised Regenerative Learning of Hierarchic Features in Spiking Deep Networks for Object Recognition,” IEEE Scar International Conference on Neural Networks (IJCNN), July 2016, Vancouver, Canada.
  4. G. Srinivasan, S. Roy, Absolutely. Raghunathan, and K. Roy, “Spike Timing Dependent Plasticity Based Enhanced Self-Learning for Efficient Pattern Cognizance in Spiking Neural Networks,” IEEE Joint International Conference on Neuronic Networks (IJCNN), May 2017.

  5. S. Sarwar, S. Venkatramani, A. Raghunathan, and K. Roy, "Multiplier-less Untruthful Neurons Exploiting Error Resiliency get something done Energy-Efficient Neural Computing," IEEE Draw up, Automation and Test in Accumulation (DATE), March 2016.
  6. P. Procyonid, G. Srinivasan, and K. Roy, " EnsembleSNN: Distributed Assistive STDP learning for Energy-Efficient Conditional Diminution in Spiking Neural Networks," IEEE Joint International Conference on Neuronic Networks (IJCNN), May 2017.

  7. P. Panda and K. Roy, “Energy Efficient and Improved Image Identification with Conditional Deep Learning,” ACM Journal on Emerging technologies satisfaction Computing, to appear.
  8. G. Srinivasan, P. Wijesinghe, S. Sarwar, Trim. Jaiswal, and K. Roy, "Significance Driven Hybrid 8T-6T SRAM reconcile Energy-Efficient Synaptic Storage in Affected Neural Networks," IEEE Design, Mechanization and Test in Europe (DATE), March 2016.

  9. Sengupta, P. Procyonid, P. Wijesinghe, Y. Kim, arena K. Roy, "Magnetic Tunnel Fusion Mimics Stochastic Cortical Spiking Neurons," Nature Scientific Reports, July 2016.
  10. J. Allred and K. Roy, “Convolving over Time via Periodic Connections for Sequential Weight Arrangement in Neural Networks,” IEEE Juncture International Conference on Neural Networks (IJCNN), May 2017.